(1) Field of the Invention
The present invention relates to the field of semiconductor manufacturing, and more specifically to a method of improving the metal stack reliability within the structure of a semiconductor.
(2) Description of Prior Art
As the technology moves to smaller dimensions, one of the most difficult obstacles to continued reductions in size is the level to level alignments in lithography, especially in complex structures of metals and contacts. Consequently, the metal packing density becomes limited by design rules that control the separation of one level of contacts from a subsequent or adjacent level, and by design rules for the tolerance of nesting of contacts or for borders used around contacts.
Contacts can be made, for instance, between an upper via and a lower metal plug, the latter having a profile in the shape of a W with the bottom of the profile being flat. The upper via may have the profile of a V. In this instance, a good contact can be made if the upper via is stacked on top of the metal plug. If the alignment of the metal via with the metal plug is poor, poor step coverage will occur and good stacked contact will be difficult to establish.
If the lower contact is made with a non-plug profile then poor alignment between the two levels of contact results in poor contact.
If the metal-plug control can be maintained, as in the damascene process, then multiple stacking of contacts can be accomplished. It is however clear that delicate and precise control of alignment between the various levels of contact is required, even where damascene type solid plugs are used within the stacking sequence.
The problem of establishing proper contact stacking is further exacerbated with the use of borderless contacts, that is contacts that have, as opposed to the above mentioned W profile, the profile that exhibits only one side. These contacts typically provide very little contact area between the upper level via and the lower level metal making for a very unreliable contact. With any misalignment, even making any contact is not assured. If the lithography misalignment is significant, the contact area is smaller still, and current crowding can occur as a results at the via contact.
With multiple levels of metalization, it is necessary to pass current from one level to another through vias. With ever-smaller design features, the size of the contact holes also shrinks and the current density in the vias can become exceedingly high. This leads to via electromigration (EM) that can be caused by poor metal step coverage or a different metal being used in the vias causing local current crowding. Either of these two reasons can cause severe contact electromigration.
The present invention addresses the case where a contact via is used and where the contact via has the above-indicated W profile. It is readily apparent that the walls of this profile are covered only with a layer (of for instance aluminum) that has a very finite thickness and that, as a consequence, causes a very heavy flow of current though the walls of the via. This high current density can be up to three to five times higher than the EM design limits and will cause early EM failure. This problem requires an improvement of the step coverage; this improvement is accomplished using Aluminum (Al) or Wolfram (W) plugs. Even with the use of plugs, however, current crowding can still occur when current goes through the plug and into the next level of (Al) wire and the current has to turn through a 90.degree. angle in order to enter the Al wire. The inner corner of the plug will in this case attract the heaviest current since this inner corner is the path of least resistance to the current.
It is clear from the above that current crowding and the subsequent EM effect can be reduced by either a proper use of the materials that come into contact with each other or by providing for a design of the interfacing surfaces that eliminates current crowding at corners within the contacting surfaces.
In addition to the above indicated design considerations for W-shaped plugs, a design objective in designing metal stack for the W-shaped plugs is to increase the EM resistance within the metal stack that is deposited on top of the metal plug. The present invention teaches methods of increasing the EM resistance of this metal stack and, in so doing, reducing the effects of electromigration.
Layers of metal are, within the Prior Art, deposited on top of the W-shaped plug. The layers of metal form the electrical interface with the metal plug. Prior Art for the formation of Wolfram plugs makes extensive use of TiN/AlCu/TiN-ARC or Ti/TiN/AlCu/TiN-ARC or TiN/Ti/AlCu/TiN-ARC or TiN/AlCu/Ti/TiN-ARC layers that are deposited on top of the metal plug in the sequence in which the materials are listed. Since AlCu forms the main part of these metal layers, the metal stack layers are referred to as AlCu metal stack layers. The present invention teaches specific processes used during the deposition of the metal stack layers.
U.S. Pat. No. 5,736,458 (Teng) shows a Ti deposition, and a N.sub.2 treatment followed by a vacuum break.
U.S. Pat. No. 5,750,439 (Naito) shows a TiON layer in a contact hole and an aluminum copper alloy line.
U.S. Pat. No. 5,543,357(Yamada et al.) discusses TiON layers in the prior art.
U.S. Pat. Nos. 5,776,830 (Sumi et al.), 5,552,339 (Hsieh) and 5,290,731 (Sugano et al.) show metal stack structures.